In the field of a semiconductor particularly a memory, methods for increasing an integration level of a device include reducing a feature size of the device and improving a cell structure. However, with the feature size scaling down, a small size transistor may generate a serious short-channel effect. Therefore, another effective solution for increasing the integration level of the device is reducing an area of a memory cell under the condition of the same feature size by improving a topological structure of the memory cell. For example, a current mainstream technology in the DRAM (Dynamic Random Access Memory) field is an introduction of a 6F2 cell instead of an 8F2 cell to enhance the integration level of DRAM remarkably. FIG. 1 is a top view of a 6F2 DRAM memory cell array, and FIG. 2 is a cross-sectional view of the 6F2 DRAM memory cell array along a line HH′ in FIG. 1. Referring to FIGS. 1-2, the 6F2 DRAM memory cell array comprises: a word line 2, a bit line 1, a contact 3 between a source region and the bit line, a capacitor contact 4, a channel region 5 formed between the capacitor contact 4 and the contact 3 between a source region and the bit line and covered by the word line 2, an isolation word line 2′, an isolation layer 6 and a data storage capacitor 7.
Compared with the 6F2 DRAM memory cell, a 4F2 DRAM memory cell has a higher storage density, and thus each of a length and a width of the 4F2 DRAM memory cell should be 2F. Because each access transistor needs to be connected with a data storage device (i.e., the data storage capacitor in DRAM), the word line and the bit line respectively, three leading-out terminals are required for each transistor. The three leading-out terminals are led out from a surface of the transistor whose source, gate and drain are constructed horizontally. As shown in FIG. 2, for the horizontal transistor structure, the length of the memory cell is at least 3F to ensure an effective isolation between transistors in an array, and consequently the 4F2 structure can not be realized.
To effectively overcome the short-channel effect as well as a leading out difficulty of the transistor of the memory cell, one solution is an introduction of a vertical transistor structure whose source, gate and drain are constructed vertically instead of the horizontal transistor structure whose source, gate and drain are constructed horizontally. The vertical transistor is fabricated on a semiconductor pillar, that is, the gate is located on a side wall of the semiconductor pillar, while the source and the drain are located in an upper end and a lower end of the semiconductor pillar respectively. Generally, the memory device such as the data storage capacitor is located on an upper end of the transistor, while the bit line is connected with a diffusion region in a lower end of the transistor. On the premise of a same occupied area of a substrate, for the vertical transistor, an effective length of the channel may be increased by enlarging a height of the semiconductor pillar so as to overcome the short-channel effect. Moreover, because the source or the drain of the vertical transistor is located in a bottom of the vertical transistor and does not need to be directly led out from the surface of the transistor, the isolation between transistors in the array may be formed more easily.
In the vertical transistor structure, the bit line (the drain) is located in the lower end of the transistor, so that it is difficult to realize a contact between the channel and the substrate (a substrate contact for short), thus causing a series of channel floating effects to affect the transistor performance. US Patent Application Publication No. 2008/0093644, “DRAM Array, Vertical Transistor Structures, and Method of Forming Transistor Structures and DRAM Arrays” published on Apr. 24, 2008, U.S. Pat. No. 7,824,982, proposes a solution of offsetting the bit line to obtain a space required for forming the substrate contact to solve the above problem. However, the offsetting of the bit line may directly result in a smaller distance between the bit line and an adjacent transistor thereof, thus causing a bad isolation and consequently a serious crosstalk. U.S. Pat. No. 6,104,061, “Memory Cell with Vertical Transistor and Buried Word and Body Line” proposes a solution of independently forming the substrate contact in a trench spaced apart from the word line to solve the above problem. However, a process thereof is complicated and unfavorable for a large scale production.
Therefore, there is a need for a high density 4F2 DRAM memory array structure of 1T1C (One Transistor One Capacitor) having good substrate contact and simple fabrication process, in which the transistor is the vertical transistor.